The present invention relates to semiconductor devices, and particularly to fabricating multi-fin fin field effect transistor (finFET) devices with merged-fin source/drains and replacement gates.
FinFETs are an emerging technology which may provide solutions to field effect transistor (FET) scaling problems at, and below, the 22 nm node. FinFET structures include at least one narrow semiconductor fin gated on at least two sides of each of the at least one semiconductor fin. FinFETs including more than one fin may be referred to as multi-fin finFETs. FinFET structures may be formed on a semiconductor-on-insulator (SOI) substrate, because of the low source/drain diffusion, low substrate capacitance, and ease of electrical isolation by shallow trench isolation structures. FinFETs may be also formed on bulk substrates to reduce wafer cost and/or enable formation of certain devices in the bulk substrate.
Due in part to the relative instability of the gate dielectric layer deposited over the finFET and work function metal layer of the gate, a replacement metal gate, or gate-last, fabrication process may be used to form multi-fin finFETs, where a sacrificial gate is formed over the semiconductor fins prior to forming source/drain regions and depositing the dielectric layer over the finFET. The sacrificial gate is later removed and replaced by a replacement metal gate (RMG) potentially including a gate dielectric layer, a work function metal layer, and a metal electrode. Because the RMG is formed after the other components of the FET, it is not subjected to various potentially damaging processing steps, for example high-temperature anneals.